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參數(shù)資料
| 型號： | ST72T774S9T1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB單片機的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的 |
| 文件頁數(shù)： | 131/144頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72T774S9T1 |
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ST72774/ST727754/ST72734
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4.7 IC SINGLE MASTER BUS INTERFACE (I2C)
4.7.1 Introduction
The I2C Bus Interface serves as an interface
between the microcontroller and the serial I2C bus.
It provides single master functions, and controls all
I2C bus-specific sequencing, protocol and timing.
It supports fast IC mode (400kHz).
4.7.2 Main Features
– Parallel bus /I2C protocol converter
– Interrupt generation
– Standard I2C mode /Fast I2C mode
– 7-bit Addressing
s
I2C single Master Mode
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
4.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I2C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I2C bus
and a Fast I2C bus. This selection is made by
software.
Mode Selection
The interface can operate in the two following
modes:
– Master transmitter/receiver
By default, it is idle.
The interface automatically switches from idle to
master after it generates a START condition and
from master to idle after it generates a STOP
condition.
Communication Flow
The
interface
initiates
a
data
transfer
and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start
condition is the address byte.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
Figure 52.
Figure 52. I2C BUS Protocol
SCL
SDA
12
8
9
MSB
ACK
STOP
START
CONDITION
VR02119B
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