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參數(shù)資料
| 型號： | ST72T754S9T1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的 |
| 文件頁數(shù)： | 83/144頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72T754S9T1 |
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ST72774/ST727754/ST72734
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16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
After a complete reading sequence, if only the CLR
register or ACLR register are read, they return the
LSB of the count value at the time of the read.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt
remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done by:
1. Reading the SR register while the TOF bit is
set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
The timer is not affected by WAIT mode.
4.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type
of level transition on the external clock pin
EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the
external
clock; thus
the
external
clock
frequency must be less than a quarter of the CPU
clock frequency.
LSB is buffered
Read MSB
At t0
Read LSB
Returns the buffered
LSB value at t0
At t0 +Dt
Other
instructions
Beginning of the sequence
Sequence completed
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