- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄195890 > ST72T754S9T1 (意法半導(dǎo)體) 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C PDF資料下載
參數(shù)資料
| 型號(hào)： | ST72T754S9T1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的 |
| 文件頁(yè)數(shù)： | 129/144頁(yè) |
| 文件大小： | 1280K |
| 代理商： | ST72T754S9T1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)當(dāng)前第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
ST72774/ST727754/ST72734
85/144
USB INTERFACE (Cont’d)
4.6.5 Programming Considerations
In the following, the interaction between the USB
interface and the application program is described.
Apart from system reset, action is always initiated
by the USB interface, driven by one of the USB
events
associated
with
the
Interrupt
Status
Register (ISTR) bits.
4.6.5.1 Initializing the Registers
At system reset, the software must initialize all
registers to enable the USB interface to properly
generate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the para-
graph titled Endpoint Initialization.
3. When addresses are received through this
channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
4.6.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of
memory whose maximum size is 48 bytes. They
can be placed anywhere in the memory space,
typically in RAM, to enable the reception of
messages. The 10 most significant bits of the start
of this memory area are specified by bits DA15-
DA6 in registers DMAR and IDR, the remaining
bits are 0. The memory map is shown in Figure 51.
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
4.6.5.3 Endpoint Initialization
To be ready to receive:
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
Note: Once transmission and/or reception are enabled,
registers EPnRA and/or EPnRB (respectively) must
not be modified by software, as the hardware can
change their value on the fly.
When the operation is completed, they can be
accessed again to enable a new operation.
4.6.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine must monitor the SOF
events and measure the interval between each
SOF event. If 3ms pass without a SOF event, the
software should set the USB interface to suspend
mode.
USB Reset (RESET)
When this event occurs, the DADDR register is
reset, and communication is disabled in all
endpoint registers (the USB interface will not
respond to any packet). Software is responsible for
reenabling endpoint 0 within 10 ms of the end of
reset. To do this you set the STAT_RX bits in the
EP0RB register to VALID.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt.
Correct Transfer (CTR)
1. When this event occurs, the hardware automat-
ically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until software clears
the CTR bit in the ISTR register, independently of
the endpoint number addressed by the transfer
which generated the CTR interrupt.
Note: If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set
to NAK.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
Note: When a CTR interrupt occurs, the TP3-TP2 bits in
the PIDR register and EP1-EP0 bits in the IDR reg-
ister stay unchanged until the CTR bit in the ISTR
register is cleared.
3. Clear the CTR bit in the ISTR register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST733C08LFK2 | 1900 A, 800 V, SCR, TO-200AC |
| ST733C08LFK1L | 1900 A, 800 V, SCR, TO-200AC |
| ST733C04LEK1 | 1900 A, 400 V, SCR, TO-200AC |
| ST733C04LEK3L | 1900 A, 400 V, SCR, TO-200AC |
| ST733C04LFK2L | 1900 A, 400 V, SCR, TO-200AC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72T774J9B1 | 制造商:STMicroelectronics 功能描述: |
| ST72T774S9T1 | 制造商:STMicroelectronics 功能描述:ST72T774S9T1 - Trays |
| ST730 | 制造商:IRF 制造商全稱:International Rectifier 功能描述:PHASE CONTROL THYRISTORS Hockey Puk Version |
| ST7-30 | 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST-7300 | 制造商:GC Electronics 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。