參數(shù)資料
型號(hào)： ST72T141K2M6XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO34
封裝： 0.300 INCH, PLASTIC, SO-34
文件頁(yè)數(shù)： 85/132頁(yè)
文件大小： 1494K
代理商： ST72T141K2M6XXX
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ST72141K
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MOTOR CONTROLLER (Cont’d)
Autoswitched Mode
In this mode the MCOMP register content is auto-
matically computed in real time as described be-
low and in Figure 35. This register is READ ONLY.
The C event has no effect on the contents of the
MTIM timer.
When a Z event occurs the MTIM timer value is
captured in the MZREG register, the previous cap-
tured value is shifted into the MZPRV register and
the MTIM timer is reset. See Figure 26.
One of these two registers (depending on the DCB
bit in the MCRA register) is multiplied with the con-
tents of the MWGHT register and divided by 32.
The result is loaded in the MCOMP compare reg-
ister, which automatically triggers the next com-
mutation (C event)
Table 18. Multiplier Result
When an overflow occurs during the multiply oper-
ation, FFh is written in the MCOMP register and an
interrupt (O event) is generated if enabled by the
OIM bit in the MIMR register.
Figure 35. Commutation Processor Block
When the timer reaches this value an RPI interrupt
is generated (timer overflow).
After each shift operation the multiply is recomput-
ed for greater precision.
Using either the MZREG or MZPRV register de-
pends on the motor symmetry and type.
The MWGHT register gives directly the phase shift
between the motor driven voltage and the BEMF.
This parameter generally depends on the motor
and on the speed.
Auto-updated Step Ratio Register: In switched
mode, the MTIM timer is driven by software only
and any prescaler change has to be done by soft-
ware (see Section 8.1.4.2 for more details).
– In autoswitched mode an auto-updated prescal-
er always configures the MTIM timer for best ac-
curacy. Figure 34 shows process of updating the
Step Ratio bits:
– When the MTIM timer value reaches FFh, the
prescaler is automatically incremented in order
to slow down the MTIM timer and avoid an over-
flow. To keep consistent values, the MTIM regis-
ter and all the relevant registers are shifted right
(divided by two). The RPI bit in the MISR register
is set and an interrupt is generated (if RIM is set).
– When a Z-event occurs, if the MTIM timer value
is below 55h, the prescaler is automatically dec-
remented in order to speed up the MTIM timer
and keep precision better than 1.2%. The MTIM
register and all the relevant registers are shifted
left (multiplied by two). The RMI bit in the MISR
register is set and an interrupt is generated if RIM
is set.
– If the prescaler contents reach the value 0, it can
no longer be automatically decremented, the
MTC continues working with the same prescaler
value, i.e. with a lower accuracy. No RMI in-
terrrupt can be generated.
– If the prescaler contents reach the value 15, it
can no longer be automatically incremented.
When the timer reaches the value FFh, the pres-
caler and all the relevant registers remain un-
changed and no interrupt is generated, the timer
clock is disabled, and its contents stay at FFh
The PWM is still generated and the D and Z de-
tection circuitry still work, enabling the capture of
the maximum timer value.
The automatically updated registers are: MTIM,
MZREG, MZPRV, MCOMP and MDREG. Access
to these registers is summarised in Table 21.
DCB bit
Commutation Delay
0
MCOMP = MWGHT x MZPRV / 32
1
MCOMP = MWGHT x MZREG / 32
MWGHT [an+1]
MZREG [Zn]
§
A x B / 32
MZPRV [Zn-1]
§
3
DCB bit
SWA bit
MCOMP [Cn+1]
§
Z
set
8
n
n-1
O
To
§ = Register updated on R event
generator
interrupt
MCRA Register
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