參數(shù)資料
型號： ST72T141K2M6XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO34
封裝： 0.300 INCH, PLASTIC, SO-34
文件頁數(shù)： 101/132頁
文件大?。?/td> 1494K
代理商： ST72T141K2M6XXX
ST72141K
70/132
MOTOR CONTROLLER (Cont’d)
Table 31. Multiplier Result
CONTROL REGISTER B (MCRB)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = VR[1:0]:
BEMF/demagnetization Refer-
ence threshold
These bits select the VREF value as shown in the
following table.
Bit 5 = CPB*:
Compare Bit for Zero-crossing de-
tection.
0: Zero crossing detection on falling edge
1: Zero crossing detection on rising edge
Bit 4 = HDM*:
Hardware Demagnetization event
Mask bit
0: Hardware Demagnetization disabled
1: Hardware Demagnetization enabled
Bit 3 = SDM*:
Software Demagnetization event
Mask bit
0: Software Demagnetization disabled
1: Software Demagnetization enabled
Bits 2:0 = OS2*,OS[1:0]:
Operating output mode
Selection bits
Refer to the Step behaviour diagrams (Figure 40,
Figure 41, Figure 42) and Table 32.
These bits are used to configure the various PWM
output configurations.
Note: The OS2 bit is the only one with a preload
register.
Table 32. Step Behaviour Summary
Note: For more details, see Step behaviour dia-
grams (Figure 40, Figure 41, and Figure 42).
* Preload bits, new value taken into account at
next C event.
DCB bit
Commutation Delay
0
MCOMP = MWGHT x MZPRV / 32
1
MCOMP = MWGHT x MZREG / 32
70
VR1
VR0
CPB*
HDM*
SDM*
OS2*
OS1
OS0
VR1
VR0
VREF Voltage threshold
0
0.2V
0
1
0.6V
1
0
1.2V
1
2.5V
Mode
OS2
bit
PWM after C
and before D
OS
[1:0]
bits
PWM after D and
before C
V
oltag
e
mod
e(V0
C1=0
)
Sen
sorle
ss
(SR
=0)
0
Same as
after D and
before C
00
On even
channels
01
On odd
channels
10
Continuous
11
All active
channels
1
Alternate
00
On even
channels
01
On odd
channels
10
Alternate odd/even
11
All active
channels
Sen
sor
(S
R=1
)
x
Unused
00
On even
channels
01
On odd
channels
10
Alternate odd/even
11
All active
channels
Cu
rrent
mode
(V0C
1=1)
S
enso
rless
(
SR=0
)
0
On even
Channels
00
On even
channels
01
On odd
channels
10
Alternate odd/even
11
All active
channels
1
On odd
channels
00
On even
channels
01
On odd
channels
10
Alternate odd/even
11
All active
channels
Se
nsor
(SR=1
)
x
Unused
00
On even
channels
01
On odd
channels
10
Alternate odd/even
11
All active
channels
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