參數(shù)資料
型號(hào)： ST72F651AR6T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 82/161頁
文件大?。?/td> 2656K
代理商： ST72F651AR6T1
ST72651AR6
27/161
Doc ID 7215 Rev 4
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 6.2.2:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 17:
■ Active Phase depending on the RESET source
■ Min 512 CPU clock cycle delay (see Figure 19
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
Figure 17. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
tw(RSTL)out
RUN
th(RSTL)in
ACTIVE
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (min 512 TCPU)
VECTOR FETCH
tw(RSTL)out
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
DELAY
1
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