參數(shù)資料
型號(hào): ST72F651AR6T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù): 56/161頁
文件大?。?/td> 2656K
代理商: ST72F651AR6T1
ST72651AR6
149/161
Doc ID 7215 Rev 4
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Figure 94. ADC Accuracy Characteristics
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB
for each 10K
Ω increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
2. Data based on characterization results with TA=25°C.
3. Data based on characterization results over the whole temperature range, monitored in production.
Symbol
Parameter
Conditions
VDD=5.5V,
2)
fCPU=1MHz
VDD=5.0V,
3)
fCPU=8MHz
1)
VDD=3.3V,
3)
fCPU=8MHz
1)
MinMax
ET
Total Unadjusted Error 1)
2.5
E0
Offset Error
-0.5
1.5
-1.0
1.5
-1.0
1.5
EG
Gain Error 1)
-2.00-2.00-2.00
|ED|
Differential linearity error 1)
1.5
|EL|
Integral linearity error 1)
2.5
3.0
EO
EG
1LSBIDEAL
1LSB
IDEAL
V
DDA
V
SSA
256
-----------------------------------------
=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
255
254
253
5
4
3
2
1
0
7
6
1
234567
253 254 255 256
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
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