參數(shù)資料
型號: ST72F611F1
英文描述: 64Mb EDO/FPM - OBSOLETE
中文描述: ST7的-低速USB 8 - 3端點(diǎn)位MCU。閃存。內(nèi)徑。水分散粒劑。定時(shí)器
文件頁數(shù): 58/161頁
文件大小: 2070K
代理商: ST72F611F1
ST72324
150/161
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
OPT7= PKG1
Pin package selection bit
This option bit selects the package.
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
OPT6 = RSTC
RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT5:4 = OSCTYPE[1:0]
Oscillator Type
These option bits select the ST7 main clock
source type.
OPT3:1 = OSCRANGE[2:0]
Oscillator range
When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
OPT0 = PLLOFF
PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequen-
cy between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
Version
Selected Package
PKG1
J
TQFP44 / SDIP42
1
K
TQFP32 / SDIP32
0
Clock Source
OSCTYPE
10
Resonator Oscillator
0
Reserved
0
1
Internal RC Oscillator
1
0
External Source
1
Typ. Freq. Range
OSCRANGE
21
0
LP
1~2MHz
0
MP
2~4MHz
0
1
MS
4~8MHz
0
1
0
HS
8~16MHz
0
1
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