參數(shù)資料
型號(hào): ST72F345N4H6
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PBGA56
封裝: 6 X 6 MM, LEAD FREE, TFBGA-56
文件頁(yè)數(shù): 47/190頁(yè)
文件大?。?/td> 3666K
代理商: ST72F345N4H6
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ST72340, ST72344, ST72345
140/190
is read when there is no communication ongoing
or by hardware when the peripheral is disabled
(PE = 0).
0: No write operation to Slave 1
1: Write operation performed to Slave 1
I2C3S INTERFACE (Cont’d)
Bit 2 = RF3 Read operation from Slave 3
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 3. It is
cleared by software reading the SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No read operation from Slave 3
1: Read operation performed from Slave 3
Bit 1= RF2 Read operation from Slave 2
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 2. It is
cleared by software reading the SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No read operation from Slave 2
1: Read operation performed from Slave 2
Bit 0= RF1 Read operation from Slave 1
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 1. It is
cleared by software reading SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No read operation from Slave 1
1: Read operation performed from Slave 1
I2C BYTE COUNT REGISTER (I2C3SBCR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = NB [7:0] Byte Count Register
This register keeps a count of the number of bytes
received or transmitted through any of the three
addresses. This byte count is reset after reception
by a slave address of a new transfer and is incre-
mented after each byte is transferred. This register
is not limited by the full page length. It is also
cleared by hardware when interface is disabled
(PE =0).
I2C SLAVE 1 ADDRESS REGISTER
(I2C3SSAR1)
Read / Write
Reset Value : 0000 0000 (00h)
Bits 7:1 = ADDR[7:1] Address of Slave 1
This register contains the first 7 bits of Slave 1 ad-
dress (excluding the LSB) and is user program-
mable. It is also cleared by hardware when inter-
face is disabled (PE =0).
Bit 0= EN1 Enable bit for Slave Address 1
This bit is used to enable/disable Slave Address 1.
It is also cleared by hardware when interface is
disabled (PE =0).
0: Slave Address 1 disabled
1: Slave Address 1 enabled
I2C SLAVE 2 ADDRESS REGISTER
(I2C3SSAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:1 = ADDR[7:1] Address of Slave 2.
This register contains the first 7 bits of Slave 2 ad-
dress (excluding the LSB) and is user programma-
ble. It is also cleared by hardware when interface
is disabled (PE =0).
Bit 0= EN2 Enable bit for Slave Address 2
This bit is used to enable/disable Slave Address 2.
It is also cleared by hardware when interface is
disabled (PE =0).
0: Slave Address 2 disabled
1: Slave Address 2 enabled
70
NB7
NB6
NB5
NB4
NB3
NB2
NB1
NB0
70
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
EN1
70
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
EN2
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