參數(shù)資料
型號(hào): ST72C171K2B6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝: SHRINK, PLASTIC, DIP-32
文件頁數(shù): 38/152頁
文件大?。?/td> 2156K
代理商: ST72C171K2B6
ST72C171
132/152
9.9 CONTROL PIN CHARACTERISTICS
9.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Figure 89. Typical Application with RESET pin 8)
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 90). This data is based on characterization results, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.
6. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environment.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2)
0.3xVDD
V
VIH
Input high level voltage 2)
0.7xVDD
Vhys
Schmitt trigger voltage hysteresis 3)
400
mV
VOL
Output low level voltage 4)
VDD=5V
IIO=+5mA
0.68
0.95
V
IIO=+2mA
0.28
0.45
RON
Weak pull-up equivalent resistor 5)
VIN=VSS
VDD=5V
20
40
60
k
VDD=3.4V
80
100
120
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
6
30
1/fSFOSC
s
th(RSTL)in External reset pulse hold time
6)
20
s
tg(RSTL)in Filtered glitch duration
7)
100
ns
RESET
VDD
WATCHDOG RESET
ST72XXX
LVD RESET
INTERNAL
RON
0.1
F
VDD
0.1
F
VDD
4.7k
EXTERNAL
RESET
CIRCUIT 8)
RESET CONTROL
O
PT
IONA
L
USER
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