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參數(shù)資料
| 型號(hào)： | ST72652R4T1 |
| 英文描述： | ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C |
| 中文描述： | ST7的-低功耗。全速USB 8位32K快閃微控制器。 5K內(nèi)存。閃存卡的I /樓計(jì)時(shí)器。脈寬調(diào)制。 ADC的。的I2C |
| 文件頁(yè)數(shù)： | 141/166頁(yè) |
| 文件大?。?/td> | 2089K |
| 代理商： | ST72652R4T1 |
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ST7265x
76/166
USB INTERFACE (Cont’d)
ENDPOINT
1
TRANSMISSION
REGISTER
(EP1TXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 1
transmission. Bits 2:0 are also reset by a USB re-
set, either received from the USB or forced
through the FRES bit in the CTLR register.
Bit 3 = CTR_TX
Correct Transmission Transfer.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1
1: Correct transfer in transmission on Endpoint 1
Bit 2 = DTOG_TX
Data Toggle, for transmission
transfers.
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by hardware, at the receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
Bits 1:0 = STAT_TX [1:0]
Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, which is listed below
Table 23. Transmission Status Encoding
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
ENDPOINT
2
RECEPTION
REGISTER
(EP2RXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling endpoint 2 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the CTLR register.
Bits 7:6 = MOD[1:0]
Endpoint 2 mode.
These bits are set and cleared by software. They
select the Endpoint 2 mode (See Figure 42 and
Notes:
1. Before selecting Download mode, software
must write the maximum packet size value (for in-
stance 64) in the CNT2RXR register and write the
STAT_RX bits in the EP2RXR register to VALID.
2. Before selecting Upload mode, software must
write the maximum packet size value (for instance
64) in the CNT2TXR register and write the
STAT_TX bits in the EP2TXR register to NAK.
70
0
000
CTR_T
X
DTOG
_TX
STAT_
TX1
STAT_
TX0
STAT_TX1 STAT_TX0
Meaning
00
DISABLED: transmission
transfers cannot be executed.
01
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
10
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
11
VALID: this endpoint is ena-
bled for transmission.
70
MOD1 MOD0
0
CTR_R
X
DTOG
_RX
STAT_
RX1
STAT_
RX0
MOD1 MOD0
Mode
00
Normal mode: Endpoint 2 is managed by
user software
01
Upload mode to USB data buffer: Bulk
mode IN under hardware control from
DTC1
10
Download mode from USB data buffer:
Bulk mode OUT under hardware control
to DTC2.
1
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