參數(shù)資料
型號(hào)： ST72141K2B3/XXX
廠(chǎng)商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 14/133頁(yè)
文件大?。?/td> 2615K
代理商： ST72141K2B3/XXX
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ST72141K2
110/133
8-BIT A/D CONVERTER (ADC) (Cont’d)
8.5.3 Functional Description
The high level reference voltage VDDA must be
connected externally to the VDD pin. The low level
reference voltage VSSA must be connected exter-
nally to the VSS pin. In some devices (refer to de-
vice pin out description) high and low level refer-
ence voltages are internally connected to the VDD
and VSS pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 63. Recommended Ext. Connections
Characteristics:
The conversion is monotonic, meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to VDD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage
≤VSS (voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Where Reference Voltage is VDD - VSS.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure:
Refer to the CSR and DR register description sec-
tion for the bit definitions.
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the “I/O Ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer to Table 45
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
s). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
8.5.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
8.5.5 Interrupts
None.
ST7
Px.x/AINx
VDDA
VSSA
VDD
0.1F
RAIN
VAIN
Digital result =
255 x Input Voltage
Reference Voltage
Mode
Description
WAIT
No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
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