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參數(shù)資料
| 型號(hào)： | ST62E85BG1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數(shù)： | 44/78頁 |
| 文件大小： | 868K |
| 代理商： | ST62E85BG1 |
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Obsolete
Product(s)
- Obsolete
Product(s)
49/78
ST62T85B/E85B
4.4.4 DATA RECEPTION
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. The data in the ninth bit position is
copied into Bit 9, replacing any previous value set
for transmission. After all 9 bits have been re-
ceived, the Receiver waits for the duration of one
bit (for the Stop bit) and then transfers the received
data into the buffer register, allowing a following
character to be received. The interrupt flag
RXRDY is set to 1 as the data is transferred to the
buffer register and, if enabled, will generate an in-
terrupt.
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
Figure 26. UART Data Output
4.4.5 INTERRUPT CAPABILITIES
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.4.6 REGISTERS
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0.
UART data bits. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer.
Warning. No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
Table 19. Baud Rate Selection
TXD1
TXD
PORT DATA
0
MUX
1
OUTPUT
UARTOE
VR02011
70
D7
D6
D5
D4
D3
D2
D1
D0
BR2
BR0
fINT Division
Baud Rate
fINT = 8MHz
fINT = 4MHz
0
6.656
1200
600
0
1
3.328
2400
1200
0
1
0
1.664
4800
2400
0
1
832
9600
4800
1
0
416
19200
9600
1
0
1
256
31200
15600
1
0
208
38400
19200
1
Reserved
49
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