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參數(shù)資料
| 型號： | ST62E18C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 8位單片機與微控制器/ D轉(zhuǎn)換器，自動重加載定時器，UART的秘書長辦公室，安全復(fù)位和20管腳封裝 |
| 文件頁數(shù)： | 22/82頁 |
| 文件大小： | 536K |
| 代理商： | ST62E18C |
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ST62T18C/E18C
RESETS
(Cont’d)
3.2.6 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the ResetVector (locat-
ed in program ROM starting at address 0FFEh). A
jump tothe beginning of theuser program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If nopending interrupt
is presentat the end of theinitialisation routine, the
MCU will continue by processing the instruction
immediately followingthe RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 15. Reset and Interrupt Processing
Figure 16. Reset Block Diagram
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
V
DD
RESET
R
PU
R
ESD1)
POWER
WATCHDOGRESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
f
OSC
RESET
ON RESET
LVD RESET
VR02107A
AND. Wired
1) Resistive ESD protection. Value not guaranteed.
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