參數(shù)資料
型號(hào)： ST62E18C
廠商： 意法半導(dǎo)體
英文描述： 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
中文描述： 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書長(zhǎng)辦公室，安全復(fù)位和20管腳封裝
文件頁(yè)數(shù)： 19/82頁(yè)
文件大?。?/td> 536K
代理商： ST62E18C
19/82
19
ST62T18C/E18C
CLOCK SYSTEM
(Cont’d)
Figure 11. Clock Circuit Block Diagram
Figure 12. Maximum Operating Frequency (f
MAX
) versus Supply Voltage (V
DD
)
Notes
:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least f
OSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystalfrequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f
OSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at f
OSG.
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
: 13
: 12
: 1
TIMER 1
Watchdog
POR
f
INT
Main Oscillator off
1
2.5
3.6
4
4.5
5
5.5
6
8
7
6
5
4
3
2
Maximum FREQUENCY (MHz)
SUPPLY VOLTAGE (V
DD
)
F
3
4
3
2
1
f
OSG
f
OSG
Min (at 85
°
C)
G
I
VR01807J
f
OSG
Min (at 125
°
C)
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