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參數(shù)資料
| 型號(hào)： | ST6246BB6/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 42/73頁 |
| 文件大?。?/td> | 1806K |
| 代理商： | ST6246BB6/XXX |
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ST62T46B/E46B
4.5 LCD CONTROLLER-DRIVER
On-chip LCD driver includes all features required
for LCD driving, including multiplexing of the com-
mon plates. Multiplexing allows to increase display
capability without increasing the number of seg-
ment outputs. In that case, the display capability is
equal to the product of the number of common
plates with the number of segment outputs.
A dedicated LCD RAM is used to store the pattern
to be displayed while control logic generates ac-
cordingly all the waveforms sent onto the segment
or common outputs. Segments voltage supply is
MCU supply independant, and included driving
stages allow direct connection to the LCD panel.
The multiplexing ratio (Number of common plates)
and the base LCD frame frequency is software
configurable to achieve the best trade-off con-
trast/display capability for each display panel.
The 32KHz clock used for the LCD controller is
derivated from the MCU’s internal clock and there-
fore does not require a dedicated oscillator. The
division factor is set by the three bits HF0..HF2 of
the LCD Mode Control Register LCDCR as sum-
marized in Table 15 for recommanded oscillator
quartz values. In case of oscillator failure, all seg-
ment and common lines are switched to ground to
avoid any DC biasing of the LCD elements.
Table 15. Oscillator Selection Bits
Notes:
1.
The usage fOSC values different from those
defined in this table cause the LCD to operate at a
reference frequency different from 32.768KHz, ac-
cording to division factor of Table 15.
2.
It is not recommended to select an internal
frequency lower than 32KHz as the clock supervi-
sor circuit may switch off the LCD peripheral if low-
er frequency is detected.
Figure 25. LCD Block Diagram
MCU
Oscillator
fOSC
HF2 HF1 HF0
Division Factor
0
1
0
1
0
Clock disabled: Display off
Auxiliary 32KHz oscillator
Reserved
1.048MHz
0
1
32
2.097MHz
1
0
64
4.194MHz
1
0
1
128
8.388MHz
1
0
1
256
Reserved
DATA BUS
CONTROL
REGISTER
LCD
RAM
SEGMENT
DRIVER
COMMON
DRIVER
VOLTAGE
DIVIDER
CONTROLLER
CLOCK
SELECTION
VLCD
1/3
2/3
VLCD VLCD
BACKPLANES
SEGMENTS
fint
OSC 32KHz
(When available)
VR02099
32KHz
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參數(shù)描述 |
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