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參數(shù)資料
| 型號： | ST6246BB6/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 13/73頁 |
| 文件大?。?/td> | 1806K |
| 代理商： | ST6246BB6/XXX |
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Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
20/73
ST62T46B/E46B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 Application Notes
No external resistor is required between VDD and
the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of VDD. The typical threshold is in the region
of 2 volts, but the actual value of the detected
threshold depends on the way in which VDD rises.
The POR circuit is NOT designed to supervise
static, or slowly rising or falling VDD.
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 12. Reset and Interrupt Processing
Figure 13. Reset Block Diagram
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
VDD
RESET
300k
2.8k
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET
ON RESET
VA0200B
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參數(shù)描述 |
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