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| 型號： | ST6245BQ1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 46/72頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ST6245BQ1 |
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ST62T45B/E45B
4.4 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of in-
dustry standard SPI specifications. The on-chip
SPI is controlled by small and simple user soft-
ware to perform serial data exchange. The serial
shift clock can be implemented either by software
(using the bit-set and bit-reset instructions), with
the on-chip Timer 1 by externally connecting the
SPI clock pin to the timer pin or by directly apply-
ing an external clock to the Scl line.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols
(I C-b
us, etc).
When data is serialized, the MSB is the first bit.
Sin has to be programmed as input. For serial out-
put operation Sout has to be programmed as
open-drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I
C-bu
s and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses. Figure 25 shows the SPI
block diagram.
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
Figure 25. SPI Block Diagram
Set Res
CLK
RESET
4-Bit Counter
(Q4=High after Clock8)
Data Reg
Direction
I/O Port
8-Bit Data
Shift Register
Reset
Load
DOUT
Output
Enable
8-Bit Tristate Data I/O
RESET
I/O Port
I/O Port
CP
CP
DIN
D0............... .............D7
to Processor Data Bus
Q4
Q4
OPR Reg.
DIN
SCL
Sin
Sout
SPI Interrupt Disable Register
SPI Data Register
Data Reg
Direction
Data Reg
Direction
DOUT
Write
Read
M0
1
Interrupt
VR01504
45
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST62T45B | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| ST6245BQ6 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| ST6263BB6 | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST6260BM1 | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
| ST62E60B | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6245BQ1/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6245BQ6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER |
| ST6245BQ6/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6245-P/QFP | 功能描述:插座和適配器 ST62 P/QFP Adaptor RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| ST6245Q1/XX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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