參數(shù)資料
型號: ST6240B
廠商: 意法半導(dǎo)體
英文描述: Replaced by PT6302 : 5Vout 3A Wide Input Positive Step-Down ISR 3-SIP MODULE -40 to 70
中文描述: 8位檢察官辦公室/存儲器與LCD驅(qū)動(dòng)器,EEPROM和一個(gè)微處理器/ D轉(zhuǎn)換器
文件頁數(shù): 43/76頁
文件大小: 1280K
代理商: ST6240B
43/76
ST62T40B/E40B
TIMER
1& 2
(Cont’d)
4.2.6 TIMER 2 Registers
Timer Status Control Register (TSCR)
Address: 0D7h
Read/Write
Bit 7 =
TMZ
: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 =
ETI
: Enable Timer Interrup
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
Bit 5 =
D5
: Reserved
Must be set to “1”.
Bit 4 =
D4
Do not care.
Bit 3 =
PSI
: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 =
PS2, PS1, PS0
: Prescaler Mux. Se-
lect.
These bits select the division ratio of the pres-
caler register.
Table 18. Prescaler Division Factors
Timer Counter Register (TCR)
Address: 0D6h
Read/Write
Bit 7-0 =
D7-D0
: Counter Bits.
Prescaler Register PSC
Address: 0D5h
Read/Write
Bit 7 =
D7
: Always read as "0".
Bit 6-0 =
D6-D0
: Prescaler Bits.
7
0
TMZ
ETI
D5
D4
PSI
PS2
PS1
PS0
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Divided by
1
2
4
8
16
32
64
128
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
615
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