參數(shù)資料
型號(hào): ST24LC21B1TR
廠商: 意法半導(dǎo)體
英文描述: Controller IC; Package/Case:14-DIP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No; Mounting Type:Through Hole
中文描述: 1kB的x8串行EEPROM的雙模式為韋莎插頭
文件頁(yè)數(shù): 13/18頁(yè)
文件大?。?/td> 149K
代理商: ST24LC21B1TR
Sequential Read.
This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode.
In all read modes
the ST24LC21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24LC21 terminate the
data transfer and switches to a standby state.
S
S
BYTE WRITE
CONTROL
BYTE
WORD ADDR
DATA
S
PAGE WRITE
WORD ADD n
DATA n
DATA n + 1
AI01505
ACK
ACK
ACK
ACK
ACK
ACK
VCLK
CONTROL
BYTE
DATA n + 7
S
ACK
ACK
Figure 11. Inhibited Write when V
CLK
= 0
13/18
ST24LC21
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PDF描述
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