參數(shù)資料
型號: ST24LC21B1TR
廠商: 意法半導體
英文描述: Controller IC; Package/Case:14-DIP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No; Mounting Type:Through Hole
中文描述: 1kB的x8串行EEPROM的雙模式為韋莎插頭
文件頁數(shù): 12/18頁
文件大?。?/td> 149K
代理商: ST24LC21B1TR
Read Operations
On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read.
The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
Random Address Read.
A dummy write is per-
formed to load the address into the address
counter, see Figure 12. This is followed by another
START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master does NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
AI01504B
S
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
VCLK
VCLK
Figure 10. Write Modes Sequence
12/18
ST24LC21
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