參數(shù)資料
型號(hào): ST16C552IJ68
廠商: STARTECH SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
中文描述: 2 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC68
文件頁(yè)數(shù): 26/39頁(yè)
文件大小: 222K
代理商: ST16C552IJ68
26
ST16C552/552A
Rev. 3.40
Logic 0 = -SLCTIN output is set to a logic 1. (normal
default condition)
Logic 1 = -SLCTIN output is set to a logic 0.
CON BIT-4:
This bit enables or masks the printer interrupt output
-INTP. The state of this bit can be read using COM bit-
4.
Logic 0 = Disable -INTP output. (normal default con-
dition)
Logic 1 = Enable -INTP output.
CON BIT-5:
This bit is used in conjunction with the state of BIDEN
to set the direction (input/output) of the PD7-PD0 data
bus.
Logic 0 + BIDEN 1 = PD7-PD0 are set for output mode
(normal default condition)
Logic 1 + BIDEN 1 = PD7-PD0 are set for input mode
CON BIT 6-7:
Not Used - initialized to a logic 1.
ST16C552/552A EXTERNAL RESET CONDITION
REGISTERS
(UART)
RESET STATE
IER
ISR
LCR
MCR
LSR
BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
FCR BITS 0-7=0
MSR
FCR
REGISTERS
Printer Port
RESET STATE
IOSEL
SR
IOSEL BITS-0-7=0
SR BITS 0-1=1, BITS 2-7=input
signals
COM BITS 0-4=0, BITS 5-7=1
CON BITS 0-5=0, BITS 6-7=1
COM
CON
SIGNALS
RESET STATE
TX A/B
-RTS A/B
-DTR A/B
INT A/B, P
-RXRDY A/B
-TXRDY A/B
PD0-PD7
-STROBE
-AutoFDXT
INIT
-SLCTIN
High
High
High
Three state mode
High
Low
Low, output mode
High, output mode
High, output mode
Low, output mode
High, output mode
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