參數(shù)資料
型號： ST16C550CJ44-F
廠商： Exar Corporation
文件頁數(shù)： 35/35頁
文件大小： 0K
描述： IC UART FIFO 16B SGL 44PLCC
標準包裝： 27
特點： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1259-5
ST16C550
9
Rev. 5.01
Table 2, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
Reserved
1
0
Modem Status Register
Reserved
1
Scratchpad Register
Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1.
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0.
With 16C550 devices, the user can set the receive
trigger level but not the transmit trigger level. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Time-out Interrupts
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-0).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger level.
In this case the ST16C550 FIFO may hold more
characters than the programmed trigger level. Fol-
lowing the removal of a data byte, the user should
recheck LSR bit-0 for additional characters. A Re-
ceive Time Out will not occur if the receive FIFO is
empty. The time out counter is reset at the center of
each stop bit received or each time the receive
holding register (RHR) is read (see Figure 10, Re-
ceive Time-out Interrupt). The actual time out value is
T (Time out length in bits) = 4 X P (Programmed word
length) + 12. To convert the time out value to a
character value, the user has to consider the com-
plete word length, including data information length,
start bit, parity bit, and the size of stop bit, i.e., 1X,
1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
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