參數(shù)資料
型號(hào)： ST16C454IJ68TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 0K
描述： IC UART QUAD 68PLCC
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 1 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC
包裝： 帶卷 (TR)
ST16C454
11
Rev. 3.31
Programmable Baud Rate Generator
The 454 supports high speed modem technologies that
have increased input data rates by employing data
compression schemes. For example a 33.6Kbps mo-
dem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input data
rate of 460.8Kbps. The 454 can support a standard data
rate of 921.6Kbps.
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
The 454 can be configured for internal or external
clock operation. For internal clock oscillator opera-
tion, an industry standard microprocessor crystal (par-
allel resonant/ 22-33 pF load) is connected externally
between the XTAL1 and XTAL2 pins (see figure 8).
Alternatively, an external clock can be connected to the
XTAL1 pin to clock the internal baud rate generator for
standard or custom rates. (see Baud Rate Generator
Programming).
The generator divides the input 16X clock by any
divisor from 1 to 216 -1. The 454 divides the basic crystal
or external clock by 16. Further division of this 16X clock
provides two table rates to support low and high data
rate applications using the same system design. Cus-
tomized Baud Rates can be achieved by selecting the
proper divisor values for the MSB and LSB sections of
baud rate generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 5 below, shows the two selectable baud rate
tables available when using a 1.8432MHz or 7.3728
MHz crystal.
Output
User
DLM
DLL
Baud Rate
16 x Clock
Program
(1.8432 MHz (7.3728 MHz
Divisor
Value
Clock)
(Decimal)
(HEX)
50
200
2304
900
09
00
300
1200
384
180
01
80
600
2400
192
C0
00
C0
1200
4800
96
60
00
60
2400
9600
48
30
00
30
4800
19.2K
24
18
00
18
9600
38.4k
12
0C
00
0C
19.2k
76.8k
6
06
00
06
38.4k
153.6k
3
03
00
03
57.6k
230.4k
2
02
00
02
115.2k
460.8k
1
01
00
01
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