- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1969 > ST16C2552IJ44TR-F (Exar Corporation)IC UART FIFO 16B DUAL 44PLCC PDF資料下載
參數(shù)資料
| 型號： | ST16C2552IJ44TR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/34頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 44PLCC |
| 標準包裝： | 500 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 3.3 V ~ 5 V |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
ST16C2552
13
REV. 4.2.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
Receive Data Shift
Register (RSR)
RXFI
16X Clock
E
rro
rT
ags
(1
6-se
ts)
E
rro
rTa
gs
in
LS
R
bi
ts
4:
2
16 bytes by 11-bit
wide FIFO
Receive Data Characters
Data Bit
Validation
RX FIFO
RHR
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
FIFO is Enabled by FCR bit-0=1
相關PDF資料 |
PDF描述 |
|---|---|
| ST16C450CJ44-F | IC UART SINGLE 44PLCC |
| ST16C450CP40-F | IC INTERFACE UART |
| ST16C452IJ68-F | IC UART W/PAR PORT DUAL 68PLCC |
| ST16C454IJ68TR-F | IC UART QUAD 68PLCC |
| ST16C550CJ44-F | IC UART FIFO 16B SGL 44PLCC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2552IQ48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| ST16C32245 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245LBR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES |
| ST16C32245TBR | 功能描述:總線收發(fā)器 14 BIT DUAL BUS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| ST16C32245TBR-E | 功能描述:開關 IC - 各種 Advanced Logic Signal Switch RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。