REV. 4.4.1 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the " />
  • 參數(shù)資料
    型號： ST16C2550IQ48-F
    廠商： Exar Corporation
    文件頁數(shù)： 13/37頁
    文件大?。?/td> 0K
    描述： IC DUART FIFO 16B 48TQFP
    標準包裝： 250
    特點： *
    通道數(shù)： 2，DUART
    FIFO's： 16 字節(jié)
    規(guī)程： RS232，RS485
    電源電壓： 2.97 V ~ 5.5 V
    帶故障啟動位檢測功能： 是
    帶調(diào)制解調(diào)器控制功能： 是
    帶CMOS： 是
    安裝類型： 表面貼裝
    封裝/外殼： 48-TQFP
    供應商設備封裝： 48-TQFP（7x7）
    包裝： 托盤
    其它名稱： 1016-1256
    ST16C2550
    20
    2.97V TO 5.5V DUART WITH 16-BYTE FIFO
    REV. 4.4.1
    4.5
    FIFO Control Register (FCR) - Write-Only
    This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
    select the DMA mode. The DMA, and FIFO modes are defined as follows:
    FCR[0]: TX and RX FIFO Enable
    Logic 0 = Disable the transmit and receive FIFO (default).
    Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
    written or they will not be programmed.
    FCR[1]: RX FIFO Reset
    This bit is only active when FCR bit-0 is a ‘1’.
    Logic 0 = No receive FIFO reset (default)
    Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
    cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
    FCR[2]: TX FIFO Reset
    This bit is only active when FCR bit-0 is a ‘1’.
    Logic 0 = No transmit FIFO reset (default).
    Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
    cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
    FCR[3]: DMA Mode Select
    Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
    Logic 0 = Normal Operation (default).
    Logic 1 = DMA Mode.
    FCR[5:4]: Reserved
    FCR[7:6]: Receive FIFO Trigger Select
    (logic 0 = default, RX trigger level =1)
    These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
    the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
    TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION
    BIT-7
    BIT-6
    RECEIVE
    TRIGGER
    LEVEL
    COMPATIBILITY
    0
    1
    0
    1
    0
    1
    1 (default)
    4
    8
    14
    16C550, 16C2552,
    16C554, 16C580 com-
    patible.
    4.6
    Line Control Register (LCR) - Read/Write
    The Line Control Register is used to specify the asynchronous data communication format. The word or
    character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
    register.
    FCR
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    參數(shù)描述
    ST16C2550IQ48TR-F 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
    ST16C2552 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
    ST16C2552_06 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
    ST16C2552CJ 制造商:EXAR 功能描述:IC , Dual UART 4MBPS 5.5 44 PLCC 制造商:Exar Corporation 功能描述: 制造商:XIC 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC
    ST16C2552CJ-0A-EB 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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