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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ST16C2550IQ48-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/37闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DUART FIFO 16B 48TQFP |
| 妯欐簴鍖呰锛� | 250 |
| 鐗归粸锛� | * |
| 閫氶亾鏁�(sh霉)锛� | 2锛孌UART |
| FIFO's锛� | 16 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232锛孯S485 |
| 闆绘簮闆诲锛� | 2.97 V ~ 5.5 V |
| 甯舵晠闅滃暉鍕曚綅妾㈡脯鍔熻兘锛� | 鏄� |
| 甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 | 鏄� |
| 甯禖MOS锛� | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-TQFP锛�7x7锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 1016-1256 |
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ST16C2550
18
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 4.4.1
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C2550 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates Transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| XR16C850CM-F | IC UART FIFO 128B 48TQFP |
| XR16L2750IM-F | IC UART FIFO 64B DUAL 48TQFP |
| ST16C2550CQ48-F | IC DUART FIFO 16B 48TQFP |
| XR88C681CP/40-F | IC UART CMOS DUAL 40PDIP |
| AT89C51RB2-RLRIM | IC MCU FLASH 8051 16K 5V 44-VQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ST16C2550IQ48TR-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 DUAL UART W/16BYTE FIFO RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| ST16C2552 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552_06 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552CJ | 鍒堕€犲晢:EXAR 鍔熻兘鎻忚堪:IC , Dual UART 4MBPS 5.5 44 PLCC 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: 鍒堕€犲晢:XIC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:UART, 44 Pin, Plastic, PLCC |
| ST16C2552CJ-0A-EB | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 Supports C2550 44 ld PLCC, ISA Interface RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭曚及:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
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