參數(shù)資料
型號: ST16C2550IP40
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S
中文描述: 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 19/34頁
文件大?。?/td> 443K
代理商: ST16C2550IP40
ST16C2550
19
Rev. 3.20
number of logic 1s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity
is generated by forcing an even
the number of logic 1s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity 1
Forced parity 0
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
This bit is used in the Loop-back mode only. In the
loop-back mode this bit is use to write the state of the
modem -RI interface signal.
MCR BIT-3: (
Used to control the modem -CD signal in
the loop-back mode.)
Logic 0 = Forces INT (A-B) outputs to the three state
mode and sets -OP2 to a logic 1. (normal default
condition)
In the Loop-back mode, sets -CD internally to a logic
1.
Logic 1 = Forces the INT (A-B) outputs to the active
mode and sets -OP2 to a logic 0.
In the Loop-back mode, sets -CD internally to a logic
0.
MCR BIT-4:
Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (-TX) and the receiver
input (-RX), -CTS, -DSR, -CD, and -RI are discon-
nected from the 2550 I/O pins. Internally the modem
data and control pins are connected into a loop-back
data configuration. In this mode, the receiver and
transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the
interrupts sources are switched to the lower four bits of
the Modem Control. Interrupts continue to be con-
trolled by the IER register.
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