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參數資料
| 型號： | ST16C2550IP40 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| 中文描述： | 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數： | 18/34頁 |
| 文件大?。?/td> | 443K |
| 代理商： | ST16C2550IP40 |
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ST16C2550
18
Rev. 3.20
Table 6, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
Not Used - initialized to a logic 0.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic
1 when the FIFOs are enabled in the ST16C2550
mode.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
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相關代理商/技術參數 |
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|---|---|
| ST16C2550IQ48 | 制造商:Rochester Electronics LLC 功能描述: |
| ST16C2550IQ48-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550IQ48TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2552 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
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