- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384931 > ST16C2550CJ44 (STARTECH SEMICONDUCTOR INC) DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S PDF資料下載
參數(shù)資料
| 型號： | ST16C2550CJ44 |
| 廠商： | STARTECH SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| 中文描述： | 2 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQCC44 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 443K |
| 代理商： | ST16C2550CJ44 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
ST16C2550
20
Rev. 3.20
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT 5-7:
Not Used - initialized to a logic 0.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 2550 and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case
the previous data in the shift register is overwritten.
Note that under this condition the data byte in the
receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the
error.
LSR BIT-2:
Logic 0 = No parity error. (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
FIFO mode, this error is associated with the character
at the top of the FIFO.
LSR BIT-3:
Logic 0 = No framing error. (normal default condition)
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s). In the FIFO mode this error is
associated with the character at the top of the FIFO.
LSR BIT-4:
Logic 0 = No break condition. (normal default condi-
tion)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO.
LSR BIT-5:
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the UART is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to CPU
when the THR interrupt enable is set. The THR bit is
set to a logic 1 when a character is transferred from the
transmit holding register into the transmitter shift
register. The bit is reset to logic 0 concurrently with the
loading of the transmitter holding register by the CPU.
In the FIFO mode this bit is set when the transmit FIFO
is empty; it is cleared when at least 1 byte is written to
the transmit FIFO.
LSR BIT-6:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode this bit is set to one
whenever the transmit FIFO and transmit shift register
are both empty.
LSR BIT-7:
Logic 0 = No Error. (normal default condition)
Logic 1 = At least one parity error, framing error or
break indication is in the current FIFO data. This bit is
cleared when LSR register is read.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the 2550 is connected to. Four bits of this
register are used to indicate the changed information.
These bits are set to a logic 1 whenever a control input
from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the 2550 has changed
state since the last time it was read. A modem Status
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C2550CP40 | Power Supply IC; Supply Voltage Max:6V; Output Voltage:1.3V; Package/Case:20-TSSOP; Leaded Process Compatible:No; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Supply Voltage Min:2.7V; Mounting Type:Surface Mount |
| ST16C2550IQ48 | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| ST16C2550 | Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) |
| ST16C2552 | Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) |
| ST16C450 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2550CJ44-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CJ44TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CP40 | 功能描述:UART 接口集成電路 DUAL UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CP40-F | 功能描述:UART 接口集成電路 DUAL UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CQ-0A-EB | 功能描述:界面開發(fā)工具 EVAL SYSTEM RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。