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參數(shù)資料
| 型號(hào)： | ST16C1551IP28 |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 18/37頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | ST16C1551IP28 |
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ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
á
REV. 4.2.0
18
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table 5
).
ISR[4]: TXRDY
This bit represents the compliment (inversion) of the TXRDY status when IER bit-5 is set to a logic 1. See
Table 1
.
ISR[5]: RXRDY
This bit represents the compliment (inversion) of the RXRDY status when IER bit-5 is set to a logic 1. See
Table 1
.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive
FIFO
reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
T
ABLE
5: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
P
RIORITY
L
EVEL
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
INTERRUPT
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
0
1
1
0
LSR (Receiver Line Status Register)
2
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
MSR (Modem Status Register)
-
0
0
0
1
None (default)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C1551IQ48 | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C2450 | 2.97V TO 5.5V DUART |
| ST16C2450CJ44 | 2.97V TO 5.5V DUART |
| ST16C2450CP40 | 2.97V TO 5.5V DUART |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C1551IQ48 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551IQ48-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2450 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:2.97V TO 5.5V DUART |
| ST16C2450_05 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:2.97V TO 5.5V DUART |
| ST16C2450CJ-0A-EB | 功能描述:界面開(kāi)發(fā)工具 Supports C2450 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
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