參數(shù)資料
型號(hào)： ST16C1551CJ28
廠商： EXAR CORP
元件分類： Serial IO/Communication Controller
英文描述： 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 4/38頁(yè)
文件大?。?/td> 622K
代理商： ST16C1551CJ28
ST16C1550/51
xr
2.97V TO 5.5V UART WITH 16-BYTE FIFO
REV. 4.2.1
12
2.7
Special (Enhanced Feature) Mode
The 155X supports the standard features of the ST16C550. In addition the 155X supports some enhanced
features not available for the ST16C550. These features are enabled by IER bit-5 and include a software
controllable (SOFT) reset, power down feature and FIFO monitoring bits.
2.7.1
Soft Reset
Soft resets are useful when the user desires the capability of resetting an externally connected device only.
MCR bit-2 can be used to initiate a SOFT reset at the RST output pin. This does not reset the 155X (only the
RESET input pin can reset the 155X). Soft resets from MCR bit-2 are “ORed” with the RESET input pin.
Therefore both reset types will be seen at the RST output pin.
2.7.2
Power Down Mode
The power down feature (controlled by MCR bit-7) provides the user with the capability to conserve power
when the package is not in actual use without destroying internal register configuration data. This allows quick
turnarounds from power down to normal operation.
2.7.3
TXRDY and RXRDY bits
When IER bit-5 is set to a logic 1, ISR bits 4 and 5 represent the compliment (inversion) of the TXRDY status
and RXRDY status, respectively. See Table 1.
FIGURE 6. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
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