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參數(shù)資料
| 型號： | ST16C1450IP28 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V UART |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 355K |
| 代理商： | ST16C1450IP28 |
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REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
5
PIN DESCRIPTIONS
N
AME
28-P
IN
PDIP
(1450)
28-P
IN
PDIP
(1451)
28-P
IN
PLCC
(1450)
28-P
IN
PLCC
(1451)
48-P
IN
TQFP
(145X)
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A0
A1
A2
21
20
19
21
20
19
21
20
19
21
20
19
30
28
27
I
Address data lines [2:0]. A2:A0 selects internal UART’s
configuration registers.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
43
45
46
47
3
4
5
6
I/O
Data bus lines [7:0] (bidirectional).
IOR#
16
15
16
15
20
I
Input/Output Read (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], places
it on the data bus to allow the host processor to read it on
the leading edge.
IOW#
14
13
14
13
17
I
Input/Output Write (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the
data byte on the data bus to an internal register pointed by
the address lines [A2:A0].
CS#
11
11
11
11
9
I
Chip Select input (active low). A logic 0 on this pin selects
the ST16C145X device.
INT
18
18
18
18
23
O
Interrupt Output (three-state, active high). INT output
defaults to three-state mode and becomes active high when
MCR bit-3 is set to a logic 1. INT output becomes a logic
high level when interrupts are enabled in the interrupt
enable register (IER), and whenever the transmitter,
receiver, line and/or modem status register has an active
condition.
MODEM OR SERIAL I/O INTERFACE
TX
10
10
10
10
8
O
Transmit Data. This output is associated with individual
serial transmit channel data from the 145X. The TX signal
will be a logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local loopback mode, the
TX output pin is disabled and TX data is internally con-
nected to the UART RX input.
RX
9
9
9
9
7
I
Receive Data. This input is associated with individual serial
channel data to the 145X. Normal received data input idles
at logic 1 condition. This input must be connected to its idle
logic state, logic 1, else the receiver may report “receive
break” and/or “error” condition(s).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C1450IQ48 | 2.97V TO 5.5V UART |
| ST16C1451CJ28 | 2.97V TO 5.5V UART |
| ST16C1451CP28 | 2.97V TO 5.5V UART |
| ST16C1451CQ48 | 2.97V TO 5.5V UART |
| ST16C1451IJ28 | 2.97V TO 5.5V UART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C1450IQ48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART |
| ST16C1450IQ48-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C1450IQ48TR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 1Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C1450IQ48TR-F |
| ST16C1451 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART |
| ST16C1451CJ28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART |
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