參數(shù)資料
型號(hào): ST10F269DIETR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, UUC
封裝: DIE
文件頁數(shù): 119/161頁
文件大?。?/td> 1595K
代理商: ST10F269DIETR
ST10F269-T3
60/160
12.2.4 - Alternate Port Functions
Each port line has one associated programmable
alternate input or output function.
– PORT0 and PORT1 may be used as address
and data lines when accessing external memory.
– Port 2, Port 7 and Port 8 are associated with the
capture inputs or compare outputs of the CAP-
COM units and/or with the outputs of the PWM
module.
Port 2 is also used for fast external interrupt in-
puts and for timer 7 input.
– Port 3 includes the alternate functions of timers,
serial interfaces, the optional bus control signal
BHE and the system clock output (CLKOUT).
– Port 4 outputs the additional segment address
bit A16 to A23 in systems where segmentation
is enabled to access more than 64K Bytes of
memory.
– Port 5 is used as analog input channels of the
A/D converter or as timer control signals.
– Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals.
If an alternate output function of a pin is to be
used,
the
direction
of
this
pin
must
be
programmed for output (DPx.y=‘1’), except for
some signals that are used directly after reset and
are configured automatically. Otherwise the pin
remains in the high-impedance state and is not
effected by the alternate output function. The
respective port latch should hold a ‘1’, because its
output is ANDed with the alternate output data
(except for PWM output signals).
If an alternate input function of a pin is used, the
direction of the pin must be programmed for input
(DPx.y=‘0’) if an external device is driving the pin.
The input direction is the default after reset. If no
external device is connected to the pin, however,
one can also set the direction for this pin to output.
In this case, the pin reflects the state of the port
output latch. Thus, the alternate input function
reads the value stored in the port output latch.
This can be used for testing purposes to allow a
software trigger of an alternate input function by
writing to the port output latch.
On most of the port lines, the application software
must set the proper direction when using an
alternate input or output function of a pin. This is
done by setting or clearing the direction control bit
DPx.y of the pin before enabling the alternate
function. There are port lines, however, where the
direction of the port line is switched automatically.
For instance, in the multiplexed external bus
modes of PORT0, the direction must be switched
several times for an instruction fetch in order to
output the addresses and to input the data.
Obviously,
this
cannot
be
done
through
instructions. In these cases, the direction of the
port line is switched automatically by hardware if
the alternate function of such a pin is enabled.
To determine the appropriate level of the port
output latches check how the alternate data
output is combined with the respective port latch
output.
There is one basic structure for all port lines
supporting only one alternate input function. Port
lines with only one alternate output function,
however, have different structures. It has to be
adapted to support the normal and the alternate
function features.
All port lines that are not used for these alternate
functions may be used as general purpose I/O
lines. When using port pins for general purpose
output, the initial output value should be written to
the port latch prior to enabling the output drivers,
in order to avoid undesired transitions on the
output pins. This applies to single pins as well as
to pin groups (see examples below).
SINGLE_BIT: BSET
P4.7
; Initial output level is "high"
BSET
DP4.7
; Switch on the output driver
BIT_GROUP:
BFLDH
P4, #24H, #24H
; Initial output level is "high"
BFLDH
DP4, #24H, #24H
; Switch on the output drivers
Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by
instructions, which do not apply to the respective port (See Chapter 6 - Central Processing Unit
(CPU)).
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