參數(shù)資料
型號: SSTV16859MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset
中文描述: SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64
封裝: 6.10 MM, MO-153, TSSOP-64
文件頁數(shù): 3/8頁
文件大?。?/td> 168K
代理商: SSTV16859MTD
3
www.fairchildsemi.com
S
Functional Description
The SSTV16859 is a 13-bit dual register with SSTL-2 com-
patible inputs and outputs. Input data is transferred to out-
put data on the rising edge of the differential clock pair.
When the RESET signal is asserted LOW all outputs are
placed into the LOW logic state and all input comparators
are disabled for power savings. Output glitches are pre-
vented by disabling the internal registers more quickly than
the input comparators. When RESET is removed, the sys-
tem designer must insure the clock and data inputs to the
device are stable during the rising transition of the RESET
signal.
The SSTL-2 data inputs transition based on the value of
V
REF
. V
REF
is a stable system reference used for setting
the trip point of the input buffers of the SSTV16859 and
other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the V
REF
signal.
Logic Diagram
For n
=
1 to 13
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