- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383835 > SSTV16859 (Fairchild Semiconductor Corporation) Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset PDF資料下載
參數(shù)資料
| 型號： | SSTV16859 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset |
| 中文描述： | 雙輸出13位的薩里衛(wèi)星技術(shù)有限公司注冊- 2兼容的I / O和復(fù)位 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 168K |
| 代理商： | SSTV16859 |
5
www.fairchildsemi.com
S
DC Electrical Characteristics
(Continued)
AC Electrical Characteristics
(Note 6)
Note 6:
Refer to Figure 1 through Figure 7.
Note 7:
This parameter is not production tested.
Note 8:
For data signal input slew rate
≥
1 V/ns.
Note 9:
For data signal input slew rate
≥
0.5 V/ns and
<
1 V/ns.
Note 10:
For CK, CK signals input slew rates are
≥
1 V/ns.
Capacitance
(Note 11)
Note 11:
T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
Symbol
Parameter
Conditions
V
DD
(V)
Min
Typ
Max
Units
R
OH
R
OL
R
O
Output HIGH On Resistance
Output LOW On Resistance
I
OH
=
20 mA
I
OL
=
20 mA
I
O
=
20 mA, T
A
=
25
°
C
2.3 to 2.7
2.3 to 2.7
7
7
20
20
| R
OH
- R
OL
|
2.5
4
Symbol
Parameter
T
A
=
0
°
C to
+
70
°
C, C
L
=
30 pF, R
L
=
50
V
DD
=
2.5V
±
0.2V; V
DDQ
=
2.5V
±
0.2V
Min
Typ
200
Units
Max
f
MAX
Maximum Clock Frequency
MHz
t
W
t
ACT
(Note 7)
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
2.5
ns
22
ns
t
INACT
(Note 7)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
22
ns
t
S
Setup Time, Fast Slew Rate (Note 8)(Note 9) (Figure 5)
Setup Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5)
Hold Time, Fast Slew Rate (Note 8)(Note 10) (Figure 5)
0.75
0.9
0.75
ns
t
H
ns
Hold Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5)
Reset Removal Time (Figure 7)
0.9
10
t
REM
ns
t
PHL
, t
PLH
Propagation Delay CK, CK to Q
n
(Figure 4)
1.1
2.8
ns
t
PHL
Propagation Delay RESET to Q
n
(Figure 6)
5.0
ns
Symbol
C
IN
Parameter
Min
2.2
Typ
Max
3.2
Units
pF
Conditions
Data Pin Input Capacitance
V
DD
=
2.5V, V
I
=
V
REF
±
310 mV
CK, CK - Input Capacitance
2.2
3.2
pF
V
DD
=
2.5V, V
ICR
=
1.25, V
I(PP)
=
360 mV
RESET
2.3
3.3
pF
V
DD
=
2.5V, V
I
=
V
DD
or GND
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSTV16859G | Voltage Regulator IC; Output Current:300mA; Package/Case:8-MSOP; Supply Voltage Max:6V; Current Rating:300mA; Leaded Process Compatible:No; Output Current Max:300mA; Output Voltage Max:5V; Output Voltage Min:1.215V |
| SSTV16859MTD | Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset |
| SSTVF16857 | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTVF16857DGG | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTVF16857DGV | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTV16859_ZAA31162 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SSTV16859_ZBA30062 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SSTV16859_ZBA31162 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SSTV16859BS | 制造商:NXP Semiconductors 功能描述:MEMORY DRIVER, 56 Pin, Plastic, LCC |
| SSTV16859BS,118 | 功能描述:寄存器 2.5V 13BT-26B SSTL2 REG BUFFER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。