參數(shù)資料
型號: SSTV16859
廠商: Fairchild Semiconductor Corporation
英文描述: Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset
中文描述: 雙輸出13位的薩里衛(wèi)星技術(shù)有限公司注冊- 2兼容的I / O和復(fù)位
文件頁數(shù): 2/8頁
文件大小: 168K
代理商: SSTV16859
www.fairchildsemi.com
2
S
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Table
L
=
Logic LOW
H
=
Logic HIGH
X
=
Don
t Care but not floating unless noted
=
LOW-to-HIGH Clock Transition
=
HIGH-to-LOW Clock Transition
Q
n-1
= Output Remains in Previously Clocked State
Pin Name
Q
1A
-Q
13A
Q
1B
-Q
13B
D
1
-D
13
RESET
CK
Description
SSTL-2 Compatible Register Outputs
SSTL-2 Compatible Register Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
V
REF
V
DDQ
V
DD
NC
Negative Master Clock Input
Voltage Reference Pin for SSTL level inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Electrically Isolated No Connect
1
2
3
4
5
6
A
B
C
D
E
F
NC
Q
12A
Q
10A
Q
8A
Q
6A
Q
4A
Q
2A
Q
1A
Q
12B
Q
10B
Q
8B
Q
6B
Q
4B
Q
2B
NC
NC
NC
Q
13A
Q
11A
Q
9A
Q
7A
Q
5A
Q
3A
Q
13B
Q
11B
Q
9B
Q
7B
Q
5B
Q
3B
Q
1B
NC
NC
NC
GND
GND
V
DDQ
V
DDQ
V
DDQ
GND
NC
GND
GND
V
DDQ
V
DD
V
DD
GND
NC
NC
NC
D
13
D
11
D
9
D
7
NC
NC
NC
D
5
D
3
D
1
NC
NC
NC
NC
NC
NC
D
12
D
10
D
8
G
RESET
H
J
K
L
M
N
P
R
T
GND
GND
V
DDQ
V
DDQ
V
DDQ
GND
GND
NC
NC
GND
V
REF
V
DD
V
DD
V
DDQ
GND
GND
NC
NC
CK
CK
NC
D
6
D
4
D
2
NC
NC
NC
RESET
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
L
H
CK
X or
Floating
H
L
Q
n
L
L
H
H
H
H
L
H
Q
n-1
Q
n-1
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