參數(shù)資料
型號： SSTV16857EV
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 14-bit SSTL_2 registered driver with differential clock inputs
中文描述： SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56
封裝： 4.50 X 7 X 0.65 MM, PLASTIC, SOT-702-1, VFBGA-56
文件頁數(shù)： 5/7頁
文件大小： 85K
代理商： SSTV16857EV
5
www.fairchildsemi.com
S
AC Electrical Characteristics (SSTV16857)
(Note 4)
Note 4:
Refer to Figure 1 through Figure 7.
Note 5:
This parameter is not production tested.
Note 6:
For data signal input slew rate
t
1 V/ns.
Note 7:
For data signal input slew rate
t
0.5 V/ns and 1 V/ns.
Note 8:
For CK, CK signals input slew rates are
t
1 V/ns.
AC Electrical Characteristics (SSTVN16857)
(Note 9)
Note 9:
Refer to Figure 1 through Figure 7.
Note 10:
This parameter is not production tested.
Note 11:
For data signal input slew rate
t
1 V/ns.
Note 12:
For data signal input slew rate
t
0.5 V/ns and 1 V/ns.
Note 13:
For CK, CK signals input slew rates are
t
1 V/ns.
Note 14:
Simultaneous Switching is guaranteed by characterization.
Symbol
Parameter
T
A
0
q
C to 70
q
C, C
L
30 pF, R
L
50
:
V
DD
2.5V
r
0.2V; V
DDQ
2.5V
r
0.2V
Min
200
Units
Max
f
MAX
Maximum Clock Frequency
MHz
t
W
t
ACT
(Note 5)
t
INACT
(Note 5)
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
2.5
ns
22
ns
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
22
ns
(not floating) after RESET LOW
Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5)
Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
t
S
0.65
0.9
ns
t
H
Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5)
Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Reset Removal Time (Figure 7)
0.75
0.9
10
ns
t
REM
t
PHL
, t
PLH
ns
Propagation Delay CLK, CLK to Q
n
(Figure 4)
1.1
2.8
ns
t
PHL
t
SK(Pn-Pn)
Propagation Delay RESET to Q
n
(Figure 6)
Output to Output Skew
5.0
200
ns
ps
Symbol
Parameter
T
A
0
q
C to 70
q
C, C
L
30 pF, R
L
50
:
V
DD
2.5V
r
0.2V; V
DDQ
2.5V
r
0.2V
Min
220
Units
Max
f
MAX
Maximum Clock Frequency
MHz
t
W
t
ACT
(Note 5)
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
2.5
ns
22
ns
t
INACT
(Note 5)
Differential Inputs De-activation Time,
Data and Clock Inputs must be held at valid levels
(not floating) after RESET LOW
22
ns
t
S
Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5)
Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5)
0.65
0.75
0.75
ns
t
H
ns
Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Reset Removal Time (Figure 7)
Propagation Delay CLK, CLK to Q
n
(Figure 4)
Propagation Delay Simultaneous Switching CLK, CLK to Q
n
(Note 14)
0.9
10
1.1
t
REM
t
PHL
, t
PLH
t
PSS
ns
ns
2.4
2.7
ns
t
PHL
t
SK(Pn-Pn)
Propagation Delay RESET to Q
n
(Figure 6)
Output to Output Skew
5.0
200
ns
ps
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相關代理商/技術參數(shù)
參數(shù)描述
SSTV16857EV,118 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTV16857EV,151 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTV16857EV,157 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTV16857EV-S 功能描述:寄存器 14BIT 2.5V REG DRV W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTV16857EV-T 功能描述:寄存器 14BIT 2.5V REG DRV W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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