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參數(shù)資料
| 型號： | SSTUAF32865AHLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 25BIT DDR2 160BGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 邏輯類型： | 1:2 寄存緩沖器，帶奇偶位 |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 位數(shù)： | 28 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 160-CABGA（9x13） |
| 包裝： | 帶卷 (TR) |
DATASHEET
2
8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAF32865A
2
8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
ICSSSTUAF32865A
7097/1
1
Description
This 28-bit 1:2 registered buffer with parity is designed for
1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load. The ICSSSTUAF32865A
operates from a differential clock (CLK and CLK). Data are
registered at the crossing of CLK going high, and CLK
going low.
The device supports low-power standby operation. When
the reset input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs except PTYERR are forced low. The LVCMOS
RESET input must always be held at a valid logic high or
low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the ICSSSTUAF32865A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The device monitors both DCS0 and DCS1 inputs and will
gate the Qn outputs from changing states when both DCS0
and DCS1 are high. If either DCS0 and DCS1 input is low,
the Qn outputs will function normally. The RESET input has
priority over the DCS0 and DCS1 control and will force the
Qn outputs low and the PTYERR output high. If the
DCS-control functionality is not desired, then the
CSGateEnable input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs.
The ICSSSTUAF32865A includes a parity checking
function. The ICSSSTUAF32865A accepts a parity bit from
the memory controller at its input pin PARIN, compares it
with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain
PTYERR pin (active LOW).
Features
28-bit 1:2 registered buffer with parity check functionality
Supports SSTL_18 JEDEC specification on data inputs
and outputs
Supports LVCMOS switching levels on CSGateEN and
RESET inputs
Low voltage operation: VDD = 1.7V to 1.9V
Available in 160-ball LFBGA package
Applications
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
Ideal for DDR2 400, 533, and 667
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| SSTUAF32866BHLF | 功能描述:IC REGIST BUFF 25BIT DDR2 96-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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