參數(shù)資料
型號: SSTUA32866EC,557
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù): 14/28頁
文件大?。?/td> 153K
代理商: SSTUA32866EC,557
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
21 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
VT = 0.5VDD.
tPLH and tPHL are the same as tPD.
VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL =VDD for LVCMOS inputs.
Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to
RESET input
tPHL
002aaa376
LVCMOS
RESET
output
VT
0.5VDD
VIH
VIL
VOH
VOL
相關(guān)PDF資料
PDF描述
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUAF32866BHLFT 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUAF32869AHLFT 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150
SSTUB32864EC/G 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
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