參數(shù)資料
型號(hào): SSTUA32864EC,557
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 鎖存器
英文描述: SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù): 20/20頁(yè)
文件大小: 117K
代理商: SSTUA32864EC,557
SSTUA32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
9 of 20
NXP Semiconductors
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM applications
10. Characteristics
Table 6.
Characteristics
Recommended operating conditions; Tamb =0 °Cto+70 °C; all voltages are referenced to GND (ground=0V);
unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = 6 mA; VDD = 1.7 V
1.2
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
0.5
V
II
input current
all inputs; VI =VDD or GND; VDD = 2.0 V
5-
+5
A
IDD
supply current
static standby; RESET = GND; IO = 0 mA;
VDD = 2.0 V
--2
mA
static operating; RESET = VDD; IO = 0 mA;
VDD = 2.0 V; VI =VIH(AC) or VIL(AC)
-
40
mA
IDDD
dynamic operating current
per MHz
clock only; RESET = VDD;
VI =VIH(AC) or VIL(AC); CK and CK switching
at 50 % duty cycle. IO = 0 mA; VDD = 2.0 V
-16
-
A
per each data input, 1 : 1 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 2.0 V
-11
-
A
per each data input, 1 : 2 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 2.0 V
-19
-
A
Ci
input capacitance
data inputs, CSR; VI =Vref ± 250 mV;
VDD = 1.8 V
2.5
-
3.5
pF
CK and CK; VICR = 0.9 V; VID = 600 mV;
VDD = 1.8 V
2-
3pF
RESET; VI =VDD or GND; VDD = 1.8 V
2
-
4
pF
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