- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98142 > SSTUA32864EC,557 (NXP SEMICONDUCTORS) SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 PDF資料下載
參數(shù)資料
| 型號： | SSTUA32864EC,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 117K |
| 代理商： | SSTUA32864EC,557 |
SSTUA32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
6 of 20
NXP Semiconductors
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM applications
6.2 Pin description
[1]
[2]
Congurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3]
Congurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
Table 2.
Pin description
Symbol
Pin
Type
Description
GND
B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3,
M4, P3, P4
ground input
ground
VDD
A4, C3, C4, E3, E4,
G3, G4, J3, J4, L3, L4,
N3, N4, R3, R4, T4
1.8 V nominal
power supply voltage
VREF
A3, T3
0.9 V nominal
input reference voltage
ZOH
J5
input
reserved for future use
ZOL
J6
input
reserved for future use
CK
H1
differential input positive master clock input
CK
J1
differential input negative master clock input
C0, C1
G6, G5
LVCMOS inputs conguration control inputs
RESET
G2
LVCMOS input
Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock differential-input receivers.
CSR, DCS
J2, H2
SSTL_18 input
Chip select inputs (active LOW). Disables data outputs
switching when both inputs are HIGH.[2]
D1 to D25
SSTL_18 input
Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
DODT
SSTL_18 input
The outputs of this register will not be suspended by DCS and
CSR control.
DCKE
SSTL_18 input
The outputs of this register will not be suspended by DCS and
CSR control.
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
1.8 V CMOS
The outputs that are suspended by DCS and CSR control[3].
QCS, QCSA,
QCSB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QODT, QODTA,
QODTB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
n.c.
A2, D2, G1
-
Not connected. Ball present but no internal connection to the
die.
DNU
-
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSTUA32866EC/G | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUAF32866BHLFT | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTUA32864EG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V configurable registered buffer for DDR2-667 RDIMM applications |
| SSTUA32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32866BHLF | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHLFT | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHMLF | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96TFBGA - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。