參數(shù)資料
型號(hào): SST89E52RC-33-C-NJE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù): 42/57頁(yè)
文件大小: 652K
代理商: SST89E52RC-33-C-NJE
Data Sheet
FlashFlex MCU
SST89E52RC / SST89E54RC
47
2007 Silicon Storage Technology, Inc.
S71259-04-000
1/07
12.1 DC Electrical Characteristics
TABLE
12-6: DC Characteristics for SST89E5xRC: TA = -0°C to +70°C; VDD = 4.5-5.5V; VSS = 0V
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
Input Low Voltage
4.5 < VDD < 5.5
-0.5
0.2VDD - 0.1
V
VIH
Input High Voltage
4.5 < VDD < 5.5
0.2VDD + 0.9
VDD + 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
4.5 < VDD < 5.5
0.7VDD
VDD + 0.5
V
VOL
Output Low Voltage (Ports 1.5, 1.6, 1.7)
VDD = 4.5V
IOL = 16mA
1.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15mA
Maximum IOL per 8-bit port:
26mA
Maximum IOL total for all outputs:71mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
VDD = 4.5V
IOL = 100A2
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise
due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
0.3
V
IOL = 1.6mA2
0.45
V
IOL = 3.5mA2
1.0
V
VOL1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80 pF.
VDD = 4.5V
IOL = 200A2
0.3
V
IOL = 3.2mA2
0.45
V
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification
when the address bits are stabilizing.
VDD = 4.5V
IOH = -10A
VDD - 0.3
V
IOH = -30A
VDD - 0.7
V
IOH = -60A
VDD - 1.5
V
VOH1
Output High Voltage (Port 0 in External Bus Mode)4
VDD = 4.5V
IOH = -200A
VDD - 0.3
V
IOH = -3.2mA
VDD - 0.7
V
IIL
Logical 0 Input Current (Ports 1, 2, 3)
VIN = 0.4V
-75
A
ITL
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches
its maximum value when VIN is approximately 2V.
VIN = 2V
-650
A
ILI
Input Leakage Current (Port 0)
0.45 < VIN < VDD-0.3
±10
A
RRST
RST Pull-down Resistor
40
225
K
Ω
CIO
Pin Capacitance6
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
@ 1 MHz, 25°C
15
pF
IDD
Power Supply Current
Active Mode @ 33 MHz
32
mA
Idle Mode@ 33 MHz
26
mA
Power-down Mode (min VDD = 2V)
TA = 0°C to 70°C
50
A
T12-6.1 1259
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