參數(shù)資料
型號(hào): SST89E52RC-33-C-NJE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù): 16/57頁(yè)
文件大?。?/td> 652K
代理商: SST89E52RC-33-C-NJE
Data Sheet
FlashFlex MCU
SST89E52RC / SST89E54RC
23
2007 Silicon Storage Technology, Inc.
S71259-04-000
1/07
Symbol
Function
COEN
Clock Divider Enable
0: Disable Clock Divider
1: Enable Clock Divider
CO_SEL
Clock Divider Selection
00b: 1/4 clock source
01b: 1/16 clock source
10b: 1/256 clock source
11b: 1/1024 clock source
CO_IN
Clock Source Selection
0b: Select clock from 1x clock
1b: Select clock from 2x clock
The default value of this bit is set during Power-on reset by copying from
Enable_Clock_Double_i non-volatile bit setting. CO_IN can be changed during normal
operation to select the double clock option.
If the clock source is a 1x clock, the clock divider exports 1/4, 1/16, 1/256, or 1/1024 of
the input clock.
If the clock source is a 2x clock, the clock divider exports 1/2, 1/8, 1/128, or 1/512 of the
input clock.
Symbol
Function
WDU
Watchdog Timer Clock Control
0:The clock for the Watchdog timer is running
1:The clock for the Watchdog timer is stopped
TCT
Timer 0/1 Clock Control
0:The Timer 0/1 logic is running
1:The Timer 0/1 logic is stopped
TCT2
Timer 2 Clock Control
0:The Timer 2 logic is running
1:The Timer 2 logic is stopped
PB2
Further Power Control 2
0:The PB2 logic is running
1:The PB2 logic is stopped
PB1
Further Power Control 1
0:The PB1 logic is running
1:The PB1 logic is stopped
Power consumption can be decreased by setting both PB2 and PB1 to 1.
UART
UART Clock Control
0:The UART logic is running
1:The UART logic is stopped
Clock Option Register (COSR)
Location
76543210
Reset Value
BFH
----
COEN
CO_SEL
CO_IN
00H
Power Management Control Register (PMC)
Location
76543210
Reset Value
A1H
-
WDU
TCT
TCT2
PB2
PB1
UART
xx000000b
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參數(shù)描述
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