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參數(shù)資料
| 型號： | SST85LP1004A-M-C-LBTE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91 |
| 封裝： | 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91 |
| 文件頁數(shù)： | 32/35頁 |
| 文件大小： | 892K |
| 代理商： | SST85LP1004A-M-C-LBTE |
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2009 Silicon Storage Technology, Inc.
S71412-02-000
10/09
6
4 GByte NANDrive
SST85LP1004A
Data Sheet
Table 1: Pin Assignments (1 of 3)
Symbol
Pin No.
Pin
Type
I/O
Type
Name and Functions
91-LBGA
Host Side Interface
A2
K8
I
I1Z
A[2:0] are used to select one of eight registers in the Task File.
A1
K3
A0
L2
D15
H8
I/O
I1Z/O2 D[15:0] Data bus
D14
G9
D13
G8
D12
H7
D11
F9
D10
F8
D9
E8
D8
F7
D7
F4
D6
H4
D5
E3
D4
H3
D3
F3
D2
G3
D1
F2
D0
G2
DMACK#
K2
I
I2U
DMA Acknowledge - input from host
DMARQ
J3
O
O1
DMA Request to host
CS1FX#
L3
II2Z
CS1FX# is the chip select for the task file registers
CS3FX#
L8
CS3FX# is used to select the alternate status register and the Device
Control register.
CSEL
L9
I
I1U
This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is configured
as a Master. When the pin is open, this device is configured as a Slave.
The pin setting should remain the same from Power-on to Power-down.
IORD#
H2
I
I2Z
IORD#: This is an I/O Read Strobe generated by the host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device.
HDMARDY#: In Ultra DMA mode when DMA Read is active, this signal
is asserted by the host to indicate that the host is ready to receive Ultra
DMA data-in bursts. The host may negate HDMARDY# to pause an
Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out strobe
generated by the host. Both the rising and falling edges of HSTROBE
cause data to be latched by the device. The host may stop generating
HSTROBE edges to pause an Ultra DMA data-out burst.
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