參數(shù)資料
型號: SST55LD019C-45-C-BWE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: LEAD FREE, MO-210, TFBGA-84
文件頁數(shù): 3/76頁
文件大?。?/td> 711K
代理商: SST55LD019C-45-C-BWE
Advance Information
ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
2004 Silicon Storage Technology, Inc.
S71241-02-000
4/04
11
SCICLK
77
52
C9
I
I3U
SCI interface clock
External Clock Option
FCE7#/
INTCLKEN
26
19
J1
I/O
I3D/O4
Active Low Flash Media Chip Enable pin
This pin is sensed during the Power-on Reset (POR) to select
an Internal Clock mode. If this pin is pulled up during the
Power-on Reset then the Internal Clock is selected.
EXTCLKIN
100
62
B3
I
I4Z
External Clock source input pin
EXTCLKOUT
99
A3
O
O4
External Clock source output pin
Miscellaneous
VSS (IO)
2
12
27
36
64
74
90
98
10
24
39
49
58
64
D7, G4
PWR
Ground for I/O
VSS (Core)
25
51
17
32
G7
PWR
Ground for Core
VDD (IO)
38
87
25
57
K4
PWR
VDD (3.3V)
VDD (Core)
76
51
B9
PWR
VDD (3.3V)
VDDQ (IO)
7
69
5
44
B1
PWR
VDDQ (5V/3.3V) for Host interface
POR#
50
30
H7
I
Analog
Input2
Power-on Reset (POR). Active Low
TIE_DN
13
D1
Pins need to be connected to VSS.
DNU3
15
16
17
18
37
47
48
49
58
59
60
61
63
81
83
85
E1
E2
F2
F3
F10
G8
G9
G10
H10
Do Not Use, must be left unconnected.
T3-1.3
1241
1. Please refer to Section 12.1 for details.
2. Analog input for supply voltage detection
3. All DNU pins should not be connected.
TABLE
3-1: PIN ASSIGNMENTS (CONTINUED) (3 OF 3)
Symbol
Pin No.
Pin
Type
I/O
Type1
Name and Functions
100-TQFP
64-TQFP
84-BGA
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