參數(shù)資料
型號(hào)： SST48CF048-C1
元件分類(lèi)： PROM
英文描述： 24M X 16 FLASH 3.3V PROM CARD, 100 ns, XMA50
封裝： CARD-50
文件頁(yè)數(shù)： 25/62頁(yè)
文件大小： 1077K
代理商： SST48CF048-C1
Data Sheet
CompactFlash Card
SST48CF008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 / 256
31
2002 Silicon Storage Technology, Inc.
S71125-03-000
2/02
375
3.1.2 Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the CompactFlash card, the registers are
accessed in the block of I/O space decoded by the system as follows:
Note: Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table.
TABLE
3-3: CONTIGUOUS I/O DECODING
-REG
A3
A2
A1
A0
Offset
-IORD=0
-IOWR=0
Notes
0
0000
0
Even RD Data
Even WR Data
1
1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don’t Care) as a word register on the combined Odd Data Bus and
Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high.
Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at
offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the Even Byte of the word and the sec-
ond byte accessed is the Odd Byte of the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses
the error (read) or feature (write) register.
0
0001
1
Error
Features
2
2. Registers at offset 8, 9, and D are non-overlapping duplicates of the registers at offset 0 and 1.
Register 8 is equivalent to register 0, while register 9 accesses the Odd Byte. Therefore, if the registers are byte accessed in the
order 9 then 8 the data will be transferred Odd Byte then Even Byte.
Repeated byte accesses to register 8 or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word
accesses to register 8, 9, or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not sup-
ported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (Even then Odd) Bytes from the
data buffer. Byte accesses to register 9 access only the Odd Byte of the data.
0
0010
2
Sector Count
0
0011
3
Sector No.
0
0100
4
Cylinder Low
0
0101
5
Cylinder High
0
0110
6
Select Card/Head
0
0111
7
Status
Command
0
1000
8
Dup. Even RD Data
Dup. Even WR Data
0
1001
9
Dup. Odd RD Data
Dup. Odd WR Data
0
1101
D
Dup. Error
Dup. Features
0
1110
E
Alt Status
Device Ctl
0
1111
F
Drive Address
Reserved
T3-3.0 375
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