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參數(shù)資料
| 型號： | SPT7853 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
| 中文描述： | 三路10位，30 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 70K |
| 代理商： | SPT7853 |
7
12/14/99
SPT7853
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line volt-
ages across part-to-part and temperature variations. By
using the configuration shown in figure 3, offset and gain
errors of less than
±
2 LSB can be obtained.
The reference ladder circuit shown in figure 4 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from V
RHF
to V
RHS
is not equivalent
to the voltage drop from V
RLF
to V
RLS
.
Typically, the top side voltage drop for V
RHF
to V
RHS
will
equal:
V
RHF
– V
RHS
= 7% of (V
RHF
– V
RLF
) (typical),
and the bottom side voltage drop for V
RLS
to V
RLF
will equal:
V
RLS
– V
RLF
= 8.8% of (V
RHF
– V
RLF
) (typical).
Figure 4 shows an example of expected voltage drops for a
specific case. V
REF
of 4.0 V is applied to V
RHF
, and V
RLF
is
tied to AGND. A 280 mV drop is seen at V
RHS
(= 3.72 V) and
a 350 mV increase is seen at V
RLS
(= 0.35 V).
ANALOG INPUT
The input voltage range is from V
RLS
to V
RHS
and will scale
proportionally with respect to the voltage reference. (See
voltage reference section.)
The drive requirements for the analog inputs are very mini-
mal when compared to most other converters, due to the
SPT7853’s extremely low input capacitance of only 5 pF
and very high input resistance of 50 k
.
The analog input should be protected through a series resis-
tor and diode clamping circuit as shown in figure 5.
V
RHF
V
RHS
V
RLS
V
RLF
+
–
+
–
All capacitors are 0.01
μ
F
Figure 3 – Ladder Force/Sense Circuit
In cases where wider variations in offset and gain can be
tolerated, V
REF
can be tied directly to V
RHF
and AGND can
be tied directly to V
RLF
as shown in figure 4. Decouple force
and sense lines to AGND with a 0.01
μ
F capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
Figure 4 – Simplified Reference Ladder Drive Circuit
without Force/Sense Circuit
Figure 5 – Recommended Input Protection Circuit
47
D1
D2
ADC
Buffer
AV
DD
+V
–V
D1 = D2 = Hewlett Packard HP5712 or equivalent
R/2
R
R
R
R
R
R
R/2
R=30
(typ)
All capacitors are 0.01
μ
F
V
RLF
(AGND)
(0.0 V)
V
RLS
(0.35 V)
V
RHS
(+3.72 V)
280 mV
350 mV
+4.0 V
External
Reference
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| SPT7855SIS | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SIT | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SPT7853SCT | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
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| SPT7855SCS | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| SPT7855SCS_Q | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| SPT7855SCT | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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