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參數(shù)資料
| 型號： | SPT7853 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
| 中文描述： | 三路10位，30 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 70K |
| 代理商： | SPT7853 |
6
12/14/99
SPT7853
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical inter-
face requirements when using the SPT7853 in normal cir-
cuit operation. The following sections provide descriptions
of the major functions and outline critical performance crite-
ria to consider for achieving the optimal device perfor-
mance.
Figure 2 – Typical Interface Circuit
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each SAR ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
follows:
Table II – Clock Cycles
Clock
1
2
3
4
5-15
16
Operation
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
11-bit SAR conversion
Data transfer
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by two clock cycles so that the
analog input is sampled on every other cycle of the input
clock by exactly one ADC section. After 16 clock periods,
the timing cycle repeats. The sample rate for the configura-
tion is one-half of the clock rate, e.g., for a 60 MHz clock
rate, the input sample rate is 30 MHz. The latency from ana-
log input sample to the corresponding digital output is 12
clock cycles.
Since only eight comparators are used, a huge power
savings is realized.
The auto-zero operation is done using a closed loop sys-
tem that uses multiple samples of the comparator’s
response to a reference zero.
The auto-calibrate operation, which calibrates the gain of
the MSB reference and the LSB reference, is also done
with a closed loop system. Multiple samples of the gain
error are integrated to produce a calibration voltage for
each ADC section.
Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
The total input capacitance is very low since sections of
the converter which are not sampling the signal are iso-
lated from the input by transmission gates.
VOLTAGE REFERENCE
The SPT7853 requires the use of a single external voltage
reference for driving the high side of the reference ladder of
each ADC. It must be within the range of 3 V to 5 V. The
lower side of the ladder is typically tied to AGND (0.0 V), but
can be run up to 2.0 V with a second reference. The analog
input voltage range will track the total voltage difference
measured between the ladder sense lines, V
RHS
and V
RLS
.
POWER SUPPLIES AND GROUNDING
The digital and the analog supply voltages on the SPT7853
are internally derived from a single analog supply. A sepa-
rate digital supply must be used for all interface circuitry
(OV
DD
). Connect the digital ground (DGND) to the analog
ground plane, as shown in figure 2, to prevent possible
latch-up condition.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the
block diagram. Each ADC uses a parallel SAR architecture.
Each contains eight identical successive approximation
ADC sections, all operating in parallel, a 16-phase clock
generator, an 11-bit 8:1 digital output multiplexer, correc-
tion logic, and a voltage reference generator which pro-
vides common reference levels for each ADC section.
+A5
+
4.7
AGND
REF IN
(+4V typ)
V
IN
1
V
IN
2
V
IN
3
4.7
+
+D2.7V-5V DGND
Enable
+D2.7V–5V
10
10
10
V
RHF
V
RHS
V
RLF
V
RLS
V
RLT
V
CAL
V
IN
A
V
IN
B
V
IN
C
A
D
V
D
OEN
DA0–9
DB0–9
DC0–9
DAV
OV
DD
CLK
S
1. Place the Ferrite bead as close to the ADC as possible.
2. All capacitors are 0.01 microfarad surface mount unless otherwise specified.
3. Place 0.01 microfarad surface mount as close to the respective decoupling pin as possible.
4. All input pins (references, analog inputs, clock input and /OEN) must be protected to
within the specified absolute maximum ratings.
NOTES:
I
L
Clock
Input
Ferrite Bead
AGND
DGND
Hi-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SPT7855 | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SCS | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SCT | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SIS | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SIT | 10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPT7853SCT | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
| SPT7855 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:10-BIT, 25 MSPS, 135 mW A/D CONVERTER |
| SPT7855SCS | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| SPT7855SCS_Q | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| SPT7855SCT | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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