參數(shù)資料
型號: SPT7850SCN
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 10-BIT, 20 MSPS, 140 mW A/D CONVERTER
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封裝: 0.300 INCH, SKINNY, PLASTIC, DIP-28
文件頁數(shù): 7/13頁
文件大?。?/td> 97K
代理商: SPT7850SCN
7
6/15/01
SPT7850
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical in-
terface requirements when using the SPT7850 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
Fairchild suggests that both the digital and the analog sup-
ply voltages on the SPT7850 be derived from a single ana-
log supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry. Fairchild suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in
the block diagram. The design contains eight identical
successive approximation ADC sections, all operating in
parallel, a 16-phase clock generator, an 11-bit 8:1 digital
output multiplexer, correction logic, and a voltage refer-
ence generator that provides common reference levels for
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in table II.
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A2
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A2
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*, 0 &=(" ! ="="9D!- =7==("C
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40 &= +B! %( !C
A2
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A
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A2
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1
2
3
4
#
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Figure 2
Typical Interface Circuit
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